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What are the differences between assignments in initial and always constructs?
Ans: While both initial and always constructs are procedural assignments, they differ in the following ways:
What are the differences between blocking and nonblocking assignments?
Ans: While both blocking and nonblocking assignments are procedural assignments, they differ in behaviour with respect to simulation and logic synthesis as follows:
What are the restrictions of using automatic tasks?
Ans: The following are the restrictions of using automatic tasks:
a. Only blocking assignments can be used on automatic variables.
b. The variables in an automatic task shall not be referenced by procedural continuous assignments or procedural force statements. In the following code, the variable my_value in the task cannot be referenced by an assign statement.
What are the rules governing usage of a Verilog function?
Ans: The following rules govern the usage of a Verilog function construct:
a. A function cannot advance simulation-time, using constructs like #, @. etc.
b. A function shall not have nonblocking assignments.
c. A function without a range defaults to a one bit reg for the return value.
What are the rules governing parameter assignments?
Ans: The rules governing the parameter assignments are as follows: The parameter override at instantiation can be done either by specifying an ordered list or by name, but not a mix of both. For example, the following is an incorrect way of specifying both width and depth.
While assigning the parameter during instantiation,once a parameter has been assigned a value, there cannot be another assignment to the same parameter. For example,specifying the width parameter twice within the same instantiation is illegal.
If a parameter is assigned both by a defparam and in the module’s instantiation, the defparam’s assignment takes precedence. In the following example,the width parameter is instantiated with value 128, but a defparam to the same parameter with the value 64 also follow sit, then the defparam gets precedence, and width will finally have the value 64.
What are the differences between using `define, and using either parameter or defparam for specifying variables?
Ans:
What is the difference between the specparam and parameter constructs?
Ans:
What are derived parameters? When are derived parameters useful, and what are their limitations?
Ans: When one or more parameters are used to define another parameter, then the result is a derived parameter. The derived parameter can be either of the type parameter or localparam. In the following example, two parameters, width and depth, can be used to define a third parameter, num_bits. In this case, the num_bits takes a value of 32.
The advantages of using derived parameters are:
a. Makes the RTL code reusable
b. Enables use of the shorter name of num_bits instead of completely specifying (width * depth)
The consequence of using derived parameters is that derived parameters can be indirectly overridden by overriding their dependent parameters through defparam constructs. So, localparam constructs should be used with care when defining derived parameters.
How is the connectivity established in Verilog when connecting wires of different widths?
Ans: When connecting wires or ports of different widths, the connections are right-justified, that is, the rightmost bit on the RHS gets connected to the rightmost bit of the LHS and so on, until the MSB of either of the net is reached. For example,
Note, however, that some simulation and synthesis tools will give a Warning when connecting nets or ports of dissimilar widths.
Can I use a Verilog function to define the width of a multi-bit port, wire, or reg type?
Ans: The width elements of ports, wire or reg declarations require a constant in both MSB and LSB. Before Verilog 2001, it is a syntax error to specify a function call to evaluate the value of these widths. For example, the following code is erroneous before Verilog 2001 version.
In the above example, get_high and get_low are both function calls of evaluating a constant result for MSB and LSB respectively. However, Verilog-2001 allows the use of a function call to evaluate the MSB or LSB of a width declaration.
What are the pros and cons of specifying the parameters?
Ans: The advantages of specifying parameters during instantiation method are:
(a) All the values to all the parameters don’t need to be specified. Only those parameters that are assigned the new values need to be specified.The unspecified parameters will retain their default values specified within its module definition.
(b) The order of specifying the parameter is not relevant anymore, since the parameters are directly specified and linked by their name.
The disadvantage of specifying parameter during instantiation are:
(a)This has a lower precedence when compared to assigning using defparam.
The advantages of specifying parameter assignments using defparam are:
(a) This method always has precedence over specifying parameters during instantiation.
(b) All the parameter value override assignments can be grouped inside one module and together in one place, typically in the top-level testbench itself.
(c) When multiple defparams for a single parameter are specified, the parameter takes the value of the last defparam statement encountered in the source if, and only if, the multiple defparam’s are in the same file. If there are defparam’s in different files that override the same parameter,the final value of the parameter is indeterminate.
The disadvantages of specifying parameter assignments using defparam are:
(a)The parameter is typically specified by the scope of the hierarchies underneath which it exists. If a particular module gets ungrouped in its hierarchy, [sometimes necessary during synthesis], then the scope to specify the parameter is lost, and is unspecified.
For example, if a module is instantiated in a simulation testbench, and its internal parameters are then overridden using hierarchical defparam constructs (For example, defparam U1.U_fifo.width = 32;).
Later, when this module is synthesized, the internal hierarchy within U1 may no longer exist in the gate-level netlist, depending upon the synthesis strategy chosen. Therefore post-synthesis simulation will fail
on the hierarchical defparam override.
How is the connectivity established in Verilog when connecting wires of different widths ?
Ans: When connecting wires or ports of different widths, the connections are right-justified, that is, the rightmost bit on the RHS gets connected to the rightmost bit of the LHS and so on, until the MSB of either of the net is reached. For example,
Note, however, that some simulation and synthesis tools will give a warning when connecting nets or ports of dissimilar widths.
Can I use a Verilog function to define the width of a multi-bit port, wire, or reg type?
Ans: The width elements of ports, wire or reg declarations require a constant in both MSB and LSB. Before Verilog 2001, it is a syntax error to specify afunction call to evaluate the value of these widths. For example, thefollowing code is erroneous before Verilog 2001 version.
In the above example, get_high and get_low are both function calls of evaluating a constant result for MSB and LSB respectively. However, Verilog-2001 allows the use of a function call to evaluate the MSB or LSB of a width declaration.
What logic is inferred when there are multiple assign statements targeting the same wire?
Ans: It is illegal to specify multiple assign statements to the same wire in a synthesizable code that will become an output port of the module. The synthesis tools give a syntax error that a net is being driven by more than one source. For example, the following is illegal:
However, it is legal to drive a three-state wire by multiple assign statements, as shown in the following example:
What do conditional assignments get inferred into?
Ans: Conditionals in a continuous assignment are specified through the “?:” operator. Conditionals get inferred into a multiplexer. For example, the following is the code for a simple multiplexer:
Figure 1.1. Conditionals infer into a multiplexer
What is the logic that gets synthesized when conditional operators in a single continuous assignment are nested?
Ans: Conditional operators in a single continuous assignment can be nested as shown in the following example. The logic gets elaborated into a tree of multiplexers.
In the multiplexer units shown, it follows the logic that when sel is high, the output Z selects A, else selects B.
Figure 1.2. Tree of multiplexers inferred from nested conditionals
What are the differences between using a task, and defining a module for implementing reusable logic?
Ans: The following table summarizes the differences between the two approaches:
Can tasks and functions be declared external to the scope of module-endmodule?
Ans: Yes. With SystemVerilog, it is possible to declare the task and function definitions external to the scope of module-endmodule. This is not possible with Verilog-1995 or Verilog-2001, and will give a compilation error. For example, in the following code, the task modify_value is declared outside the scope of the module-endmodule.
Similarly, with SystemVerilog, a function-endfunction can also be declared outside the scope of module-endmodule within the same file. If these contents are defined in a separate file, it needs to be part of the same compilation command.
What are the considerations to be taken choosing between flop-flops vs. latches in a design?
Ans: Both latches and FFs have their relative advantages and disadvantages in their implications, as summarized in the table below:
Which one is better, asynchronous or synchronous reset for the storage elements?
Ans: The following table summarizes the comparison between using synchronous and asynchronous reset logic for a design:
How do I choose between a case statement and a multi-way if-else statement?
Ans: Both case and if-else are flow control constructs. Functionally in simulation they yield similar results. While both these constructs get elaborated into combinatorial logic, the usage scenarios for these constructs are different.
(a) A case statement is typically chosen for the following scenarios:
When the conditionals are mutually exclusive and only one variable controls the flow in the case statement. The case variable itself could be a concatenation of different signals.
(b) To specify the various state transitions of a finite state machine. Use of casex and casez allows use of x and z to represent don’t-care bits in the control expression.
A multi way if statement is typically chosen in the following scenarios:
(a) Synthesizing priority encoded logic.
(b) When the conditionals are not mutually exclusive and more general in using multiple expressions for the condition expression.
The advantages of using the case over if-else is as follows:
(a) case statements are more readable than if-else.
(b) When used for state machines, there is a direct mapping between the state machine’s “bubble diagram” and the case description.
In a case construct, if all the possible cases are not specified, and the default clause is missing, a latch is inferred. Likewise, for an if-else construct, if a final else clause is missing, a latch is inferred.
How do I avoid a priority encoder in an if-else tree?
Ans: An if-else tree may synthesize to a priority encoded logic. For example, the following code produces a priority encoder:
In simulation, the if-else-if series is evaluated in the order listed. If in0 and in1 were both true, the in0 branch would be taken, because in0 is evaluated first. Synthesis tools will create a priority encoded logic in this example, so that the logic generated will behave the same as the RTL simulation.
What are the differences between if-else and the (“?:”) conditional operator?
Ans: The following table summarizes the differences between the two flow control constructs, that is, conditional “?:” and the if-else.
What is the importance of a default clause in a case construct?
Ans: The default clause in a case statement indicates that when all other cases are not met, then the flow can branch to the statements in the default clause.This gives the synthesis tool an option to pick a branch when no othercondition is satisfied. If the default clause is missing, the logic will have to remember what the output was earlier, and hence a latch will get synthesized. For example, the following case statement will generate a latch:
In the above, with the two lines commented, a latch gets synthesized for out1 register. Un-commenting either the default clause or the last condition of 2’b11, or both, will result in the combinatorial logic of a multiplexor to be synthesized.
What is the difference between full_case and parallel_case synthesis directive?
Ans: The difference between full case and parallel case synthesis directives is summarized in the table below:
What is the difference in implementation with sequential and combinatorial processes, when the final else clause in a multiway if-else construct is missing?
Ans: The results are different, depending upon whether the if statement is a part of a sequential always block or a combinatorial always block.
In a combinatorial always block, when the final else clause in a multiway if-else statement is missing, it will infer a latch. The latch is inferred because the register has to remember the value until it is reloaded again. For example,
In a sequential always block, if the final else clause in a multi-way if-else statement is missing, it will still go ahead and infer the flip-flop, with the combinatorial inference of the logic in the D input of the flop. For example,
The above code will infer logic, as shown below. The D input to the flop is now a simple gated function of the inputs.
Figure 2-9. Logic inference of if statement without final else in a FF
What is the difference in using (== or !=) vs. (===or !==) in decision making of a flow control construct in a synthesizable code?
Ans: In Verilog, the (==) operator is called logical equality, and (!=) is called logical inequality operator. The (===) operator is called case equality, and (!==) is called case inequality. The following are the differences in using these constructs in synthesizable code.
Explain the differences and advantages of casex and casez over the case statement?
Ans: The casex operator has to be used when both the high impedance value (z) and unknown (x) in any bit has to be treated as a don’t-care during case comparisons. The casez operator treats the (z) operator as a don’t-care during case comparisons.
In both cases, the bits which that are treated as don’t-care will not be considered for comparison, that is, only bit values other than don’t care bits are used in the comparison. The wildcard character “?” can be used in place of “z” for literal numbers.The following is an example of a casex statement.
The same example, if written with an if-else tree, would look like:
Using casex or casez has the following coding advantages:
(a) It reduces the number of lines, especially if the number of bits had been more.
(b) Makes code look more clear and less cluttered.
(c) Simplifies the optimization, as it is clear that the bits with x are to be ignored.
Illustrate the differences between Mealy and Moore state machines.
Ans: Both Mealy machine and Moore machine are two commonly used coding styles of state machines. The basic block diagram of these two state machines are shown as follows:
Illustrate the differences between binary encoding and onehot encoding mechanisms state machines.
Ans: The encoding in state machines are primarily either binary [sometimes called sequential] encoding or the one-hot encoding. Both mechanisms eventually lead to decoding of the states, but their logic implementation,timing and area implications differ. The differences are summarized in the table as follows:
Explain a reversed case statement, and how it can be useful to infer a one-hot state machine?
Ans: The case expression need not necessarily be a variable. When a constant is used in a case expression, the value of the constant expression will be compared against each of the case item expressions. This is called a reversed case statement. This coding style fits the one-hot state machine scenario very well.
In the following code, a one-hot state-machine is illustrated, using reversed case statement. Since the case statement expression will cause entry into the case statements for any value, the first case item that matches will cause the exit from the case statement.
What are the considerations in instantiating technology specific memories?
Ans: Instantiating technology specific memories are required in many applications.
Depending upon the application, the choice of memory is based on the following performance variables:
Area: If the area is the prime concern on the die, then a high-density memory is required. This is typically targeted for high volume applications or chips with large on chip memory blocks. The overall area will also depend upon the process technology of the memory
block.
Frequency: If the speed is the prime concern, then high-speed memories are required which operate at high frequencies. Note that these memories could potentially be larger in area.
Power: This is one of the critical concerns for low voltage and low power applications of chips in cellular phones, hand held devices, etc. Also, if the power dissipation becomes high, then the operating conditions begin to be de-rated, to the extent that the performance of the overall system becomes lower. It also increases the cost of final
packaging of the chip for dissipation purposes. Note that power dissipation is tightly coupled with the frequency at which the memory will be used.
Capacity: The capacity of the memory is typically specified in the resolution of bits. For example, a memory is specified as 512Kbits.
Voltage: Since some memories are designed for specific voltage ranges, it is important to pick the memory meeting the desired voltage ranges.
Synchronous or asynchronous: This variable specifies whetherthe memory will have a synchronous read/write or an asynchronous read/write. Which one is to be used primarily
depends upon the presence of a clock element, and the matching of timing requirements of the memory and the design.
Single port or multi port: This variable determines whether the storage within the memory is accessed by a single read/write port or multiple ports. One of the critical issues during the use of a multi-port memory is the resolution on what happens when multiple ports are trying to do a write to the same memory location.
Flip-flop or latch based: This variable determines if the storage element within the memory is based on a flip-flop or the latch. The important considerations for this memory are the testability and power. Note that a FF based design is more testable than a latch based design.
Scannable or not: With the size of the memory increasing nowadays, the scannability of the memory is an important criteria. Many manufacturers and vendors are providing the BIST logic for making the memory scannable.
Unit cost: This variable will eventually drive the overall cost of the chip, board, and the system itself. It matters a lot in a mass production scenario.
Availability: Availability of the memories will impact the time to market for the end-product success.
Failure rate: The yield of the memory must be high, and the failure rate must be low. BIST circuits will be required to be added within the chip, along with the memories to test them.
What are the factors that dictate the choice between synchronous and asynchronous memories?
Ans:
What are some reusable coding practices for RTL Design?
Ans: A reusable design mainly helps in reducing the design time of larger implementations using IPs.The following key points summarize the main considerations during the implementation phase:
(a) Register all the outputs of crucial design blocks. This will make the timing interface easy during system level integration
(b) If an IP is being developed in both Verilog and VHDL, try to use the constructs that will be translatable later into VHDL.
(c) Avoid snake paths, as it will make both debugging tedious and synthesis inefficient.
(d) Partition the design considering the clock domains and the functional goals.
(e) Follow lexical and naming conventions that are self-descriptive and facilitate future product maintenance.
(f) Avoid instantiation of technology specific gates
(g) Use parameters instead of hard-coded values in the design
(h) Avoid clocks and resets that are generated internal to the design
(i) Avoid glue logic during top level inter-module instantiations
What are “snake” paths, and why should they be avoided?
Ans: A snake path, as the name suggests is a path that traverses through a number of hierarchies, and may eventually return back to the same hierarchy from which it originated.
Snake paths must be avoided in a design for the following reasons:
It will constitute a long timing path, and hence, be the surprise critical path when static timing analysis is done at the top level. It may not show up during the timing analysis of the unit level blocks ifit is poorly constrained.
The synthesis tools need to put more effort in characterizing the constraints of the path across
the hierarchies, and the compile time can get higher.
Register the outputs of modules with different functional objectives.
Partition the design functionally, to avoid long paths across different hierarchies.
What are a few considerations while partitioning large designs?
Ans: A large design needs to be approached in a hierarchical fashion. The following considerations need to be taken while partitioning these designs:
Functionality: The functional grouping of the logic within a hierarchy is the prime criteria during partitioning the design. Typical partitioning of hierarchies are:
(a) Address and data paths: This module typically contains the address and data path registers, which drive the address and data buses of the primary outputs.
(b) Control logic: This module typically contains Finite State Machines (FSMs), and the module gets the inputs for the FSMs, whose outputs drive the controls for the rest of the logic.
Clock domains: In a multiple clock design, it is recommended to group the logic connected in the same clock domain in a single module. When signals need to interact with another module with a different clock, it is recommended to go through a synchronizer module, which takes in the input from the source clock domain and synchronizes it to the clock
domain of the destination module.
Area: Having too little logic in a module will create too many hierarchies, and too much logic within a single module will create issue of not being able to do fine tune control during floorplanning later during the backend process.
What is a safe strategy to transfer data of different buswidths and across different clock domains?
Ans: When data is to be transferred across different bus width and different clock domains, a FIFO (First In First Out) is an ideal component. If the bus width between the write (the side which pushes the data into the FIFO) and read (the side which pops the data from the FIFO) sides are different, then it becomes an asymmetrical FIFO. Many IP and chip vendors have asymmetrical and dual clock FIFOs in their libraries. An entity diagram of a typical asymmetrical and dual clock FIFO is shown in the following figure:
Figure 1.5. Assymmetrical width FIFO
The flags in the FIFO above are typically the full, empty, almost-full and almost-empty. The thresholds for these FIFOs can either be set as an input signal or as an instantiating parameter. The widths of the wr_data and rd_data busses are different, but are usually related by an integral multiple (that is, one width is an integral multiple of the other).
What are a few considerations while using FIFOs for posted writes or prefetched reads that influence the speed of the design?
Ans: FIFOs are typically used in numerous data transfer applications for performance and sustenance reasons. One of the main applications of FIFOs is to post write transactions and to prefetch the data reads.
The advantages of using the FIFOs for posted writes or prefetched reads
are:
(a) FIFOs in general help as a temporary storage buffer, which stores the data written from the write path until it is popped out by the consumer. Thus, in an application like a bridge across two protocol buses with different frequencies, FIFOs help in completing the bus cycles of a faster host sooner. This allows other masters in the host bus to use the bus more efficiently.
(b) The performance of write data transfer from a bridge that is faster is a lot better when it stores the data in the FIFO, as it doesn’t have to be held up by a slower slave through wait states during the individual beats of the data transfer.
The disadvantage of using the FIFOs for posted writes or prefetched reads are:
(a) Suppose the originating master posts the data into the FIFO, and assumes the data transfer to have happened to the destination slave, and the slave now issues an ERROR. It has to be communicated back to the master, since it assumes the data transfer to have taken place. Typically, in SoC environments, it is taken care of by issuing a high priority
interrupt to the host or the originating master.
(b) If the originating master aborts a read transaction late in the cycle when the read prefetch has already taken place, there is a possibility of a stale data remaining in the read FIFO. When such a condition occurs, the read FIFO may need to be flushed before a new read transaction.
(c) In order to ensure data coherency between a read followed by write situation, all reads to the same slave address space must be blocked until the previous write transaction is completed. This is typically monitored by watching the empty signal of the FIFO.
What will be synthesized of a module with only inputs and no outputs?
Ans: A module with only inputs and no outputs will synthesize into a module with no logic, since there is nothing to be synthesized as an output.
Why do I see latches in my synthesized logic?
Ans: There is more than one reason why latches could be seen in synthesized
logic. This information is typically present in the elaboration log file of the synthesis tool.
(a) The if-else clause in the always block to which the latch is associated doesn’t have a final else clause.
(b) The reg declaration of the variable doesn’t have any value assigned upon entry to the combinatorial always block if the variable is used in an if statement without the else clause.
(c) There could be no default clause of a case construct that is not complete or the variables assigned within the case were not assigned a default value before entering the case statement.
What are “combinatorial timing loops”? Why should they be avoided?
Ans: Combinatorial timing loops are hardware loops in which the output of either a gate or a long combinatorial path is fed back as an input to the same gate or to another gate earlier in the combinatorial path. These paths are generally created unintentionally when a variable from one combinatorial block is used to drive a signal that is used in the same combinatorial block from which the variable was derived. This typically happens in large size combinatorial blocks, wherein it is difficult to visually track that a loop is getting created.
These combinatorial feedback loops are undesirable for the following reasons:
(a) Since there is no clock edge in between to break the path, the combinatorial loops will infinitely keep oscillating and triggering a square waveform, whose duty cycle is dependent upon the sum of ON delays and OFF delays across the combinatorial path. For example, the following code is a combinatorial loop:
This will cause the out1 to feed in combinatorially back as one of the inputs.
(b) These loops cause a problem in testability, since they can inhibit the propagation of the logic forward.
Combinatorial loops can be caught quite early by one of the following means:
(c) Periodic use of linting tools throughout the development process.This is by far the best and easiest way to catch and fix loops early in the design cycle.
(d) During functional simulation, the desired output behavior doesn’tappear in the output, or the simulation doesn’t proceed ahead at all,because the simulator is hung.
(e) If the loop is undetected during simulation, many synthesis tools have suitable reporting commands, which detect the presence of a loop. Note that synthesis tools proceed with the static timing analysis by breaking the timing arc of the loop for critical path analysis.
What happens to the bits of a reg which are declared, but not assigned or used?
Ans: When any of the bits of a reg declaration is unused, the logic corresponding to those bits gets optimized away. For example, in the following code, the bits 2:1 are unused, although the int_tmp is declared to be [3:0]. This code will synthesize the logic for bits [3] and [0], and no logic for bits [2:1]
What is the difference between using `ifdef and generate for the purpose of area minimization?
Ans:
Can the generate construct be nested?
Ans: No. The generate construct cannot be nested. It is a syntax error to try to nest the generate-endgenerate construct.
However, the if, case, and for constructs within the generateendgenerate can be nested. The constructs can also be used within one another, too, that is, if within case, for within if etc.
You can also use multiple non-nested generate-endgenerate constructs within the module.
How do the `ifdef, `ifndef, `elsif, `endif constructs aid in minimizing area?
Ans: The proper use of compiler directives like `ifdef, `ifndef, etc. can help in minimizing the area during post elaboration and during logic optimization. Since the use of compiler directives is a compile time operation, it is a static decision for the session of simulation and during synthesis. The following is an example of how the compiler directives can be used for minimizing the area of a logic design.
Note that the use of compiler directives is legal to pick instantiations of modules itself, and, hence, can be helpful to pick a module with appropriate area size. For example, in the following code, the compiler directive is used to pick the correct type of counter, that is, ripple counter or carry lookahead, counter depending upon the directive.
In the above example, the `ifndef was used to illustrate the absence of a `define for CLA. Note that the `define for CLA has been commented out. If it gets uncommented, then the carry lookahead adder instantiation gets selected.
Hence, in this approach, the selection of the appropriate “section” of code during parsing and elaboration decides the final area of implementation.
What is “constant propagation”? How can I use constant propagation to minimize area?
Ans: Constant propagation is a very effective technique for area minimization, since it forces the synthesis tools to optimize the logic in both forward and backward directions. Since the area minimization is achieved using constants, this technique is called constant propagation. An example of constant propagation is shown below:
Note that create_logic is a parameter within the module, that controls the logic backwards from both the outputs out1 and out2. It could also control the logic forward from the inputs in1 and in2 by adding internal wires to either select the direct input in1 or the 1’b0. An example of how the forward constant propagation works is as follows:
When this parameter is 0, it forces the logic zero in the assign statements, it results in logic zero propagation in either direction. As a result, no logic gets enabled and the logic is optimized in synthesis. When this parameter is 1, the logic is synthesized.
Note that different techniques to override the parameter will also work, that is, the constant propagation will be effective, even with parameter override.
Hence, the default value of the parameter can be set to 1, and be overridden to 0, by different parameter overriding techniques, when required to minimize the area.
SystemVerilog has also introduced a new construct const which declares a variable as a constant. The const construct can be used to enforce constant propagation, just like other constants like parameter. For example, the same example above can be applicable by replacing the parameter with const, as follows:
What is a critical path in a design? What is the importance of understanding the critical path?
Ans: A critical path is the path through a circuit that has the least slack. It is not necessarily the longest path in the design. There can be more than one critical path in a design. In fact, all paths whose difference between the arrival time and required time at the endpoint is negative (, that is, negative slack) is a violating path.
Understanding and identifying the critical path in a design is important for the following reasons:
(a)It helps fix the static timing problems, especially when the endpoint is a D input to a flip-flop, and the critical path delay is violating the setup time requirement for the flop.
(b)Shortening the critical path delay obviously improves frequency and,hence, the performance of the logic.
(c)If the critical path is identified early in the design flow, then appropriate functional changes can be done early on in the project to terminate the path to the D input of a flop at an appropriate point in the path. This point has to be carefully chosen, considering the side effects in latency and static timing that would arise due to the staging of the path through a flop.
(d)If the source of the critical path is from a primary input, it is recommended to register the input. Although this could add to the latency, this strategy will eventually help in improving the frequency of operation.
How does proper partitioning of design help in achieving static timing?
Ans: Partitioning a design correctly helps in multiple stages of the design, all the way until the backend flow. The best approach for partitioning is to plan the partitioning of the design before writing HDL code. It is important to keep these considerations early on, to avoid hierarchical, port, or logic changes late in the design. The following are some of the criteria for design partitioning:
a.Logical partitioning: The partitioning of the modules with close logical associativity is a very common approach. This way, it is both easy to debug and modular in approach. Typically, the partitioning logic boundaries are datapaths (register’s and glue), control (FSMs), memories and I/O. Logistically, it also helps with having multiple team members do thorough unit level verification, and it helps with better design management and version control. All combinatorial logic associated with the same clock domain should also be closely within the same module. Inter-module partitions can restrict logic
optimization by synthesis tools. Hierarchical boundaries prevent any combining of related logic. Typically, a module size should be around 5K gates.
For synthesis tools to consider resource sharing and freedom to optimize, all relevant resources need to be within one level of hierarchy. If the resources are not within one level of hierarchy, synthesis tools cannot make tradeoffs to determine whether or not
the resources should be shared. It is during the logical partitioning that the designer has the freedom to decide upon the registering of the outputs between critical intermodule
hierarchies. This will immensely reduce the possibilities of long combinatorial paths and combinatorial snake paths in the design, and, hence, better static timing implication.
Special function logic, like the pads, I/O drivers, clock generation and boundary scan should be at separate logical hierarchies. Any on-chip memories, like SRAMs or DRAMs should be placed at the top level. This will make the physical design interaction and floorplanning tasks more effective by better timing analysis.
b.Goal based partitioning: Partitioning based on different design goals of speed and area will eventually help the tools do a good job. Modules with different goals can be specified with their respective constraints during the synthesis for the tools to do a good job.
Clock domain partitioning: Partitioning the logic according to same clock domain plays an important role in synthesis, static timing analysis, and scan insertion. The inter-clock false paths can be defined within a single synchronizer module, and the entire module
is now with a single clock domain.
c.Reset based partitioning: If a particular SoC has multiple resets, then it is a good idea to consider reset based partitioning, too. This helps all the storage elements within the module to wake up gracefully at the same time.
What does it mean to “retime” logic between registers? How does it effect functionality?
Ans: Retiming is the process of relocating registers across logic gates, without affecting the underlying combinatorial logic structure. This process is achieved by borrowing logic from one time frame and lending it to the other, while maintaining the design behavior. When you have a pipelined design, for example, in a datapath of a design, then retiming is a technique for reducing the critical path within the pipeline.
Retiming has benefits as follows helps in balancing the paths between the pipeline stages
Retiming also has potential restrictions as follows:
a. Note that, although retiming can be used to reduce the critical path between the pipeline registers, it cannot be used to reduce the latency of the design.
b. A retimed design may not be formally equivalent to the original design.
Why is one-hot encoding preferred for FSMs designed for high-speed designs?
Ans: Since there is one explicit FF per stage of a one-hot encoded state machine, there is no need of output state decoding. Hence, the only anticipated delay is the clock to q delay of the FF. This makes the one-hot encoding mechanism preferable for high-speed operation.
Ans: While both initial and always constructs are procedural assignments, they differ in the following ways:
the differences between continuous and procedural assignments?
Ans: The following table captures the differences between continuous and procedural assignments:
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