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What is p_sequencer and m_sequencer?
Ans:
p_sequencer :
The p_sequencer is a type specific sequencer pointer, created by registering the sequence to a sequencer using the `uvm_declare_p_sequencer macros. Being type specific, you will be able to access anything added to the sequencer (i.e. pointers to other sequencers, etc.).
p_sequencer will not exist if the `uvm_declare_p_sequencer macros isn’t used. (Does not exist by default).
The term p_sequencer refer to physical sequencer.
m_sequencer :
m_sequencer is the handle of uvm_sequencer_base class.
m_sequencer is present by default in every sequence (virtual sequence)
m_sequencer and p_sequencer are used for the type casting.
What is a UVM RAL model? Why is it required?
Ans:
UVM RAL as the name suggests, is a high-level object-oriented abstraction layer to access design registers. RAL model mimics the design registers and this entire model is fully configurable. Due to its abstraction behaviour, RAL model can be easily migrated from block level to system level.
RAL model mimics the design register, value by which design register is updated, with the same value RAL model register is also updated.
What is an analysis port ?
Ans:
The analysis port is used to perform non-blocking broadcasts of transactions. It is by components like monitors/drivers to publish transactions to its subscribers, which are typically scoreboards and response/coverage collectors. For each port, more than one component can be connected. Even if a component is not connected to the port, simulation can continue, unlike put/get ports where simulation is not continued.
The uvm_analysis_port consists of a single function, write(). Subscriber component should provide an implementation of write()method. UVM provides the uvm_subscriber base component to simplify this operation, so a typical analysis component would extend uvm_subscriber and its export is analysis_export.
What is the difference between new() and create() ?
Ans:
new() is the native constructor function in SystemVerilog, and is not UVM specific. You need to use with SV-specific classes like mailbox and semaphore. create() is the factory method used to construct objects of classes derived from uvm_object and uvm_component when using UVM. Function create() has some advantages but is a bit more complex to use and setup. It works only if a class has been registered with the factory, normally using UVM macros uvm_component_utils… and uvm_object_utils… . When using create(), it is possible to override the created type at runtime and thus create another type of object. This is not possible with new() .Unless you really want someone to prevent using type overrides, you can use create() by default, and only use new() if you have very good reason to do so, or if you are creating non-UVM objects.
Is UVM independent of SystemVerilog ?
Ans:
No, uvm is built on SV and hence you cannot run UVM with any tool that does not support SV.
Why do we need to register a class with a factory?
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Having registered your objects and components with the factory, you can now make requests for new objects and components via the factory. Using the factory instead of allocating them directly (via new) allows different objects to be substituted for the original without modifying the requesting class.
What are Active and Passive modes in an agent ?
Ans:
Active: monitor, sequencer and driver are present to stimulate and observe the data
Passive: monitor is only present to observe data
What is a TLM Fifo ?
Ans:
Provide storage for the transactions between the 2 independently running processes.
Fifo can be used as a buffer between the producer and consumer
Fifo consists of put and get methods
Producer port is connected to the put_export of the fifo
Consumer port is connected to the get_export of the fifo
What are the advantages of `uvm_component_utils and `uvm_object_utils ?
Ans:
Both `uvm_object_utils and `uvm_component_utils are macros that are used to register UVM objects and UVM components respectively with the factory. If a component/object is registered with the factory, it can be easily overridden using methods like type_override. Also, when a component/object is registered with the factory, they also implement few functions like copy, print, etc.
How does a sequence start ?
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The sequence will get executed upon calling the start of the sequence from the test. sequencer_name specifies on which sequencer sequence has to run.
sequence_name.start(sequencer_name);
What are the different phases in UVM?
Ans:
Build, connect, end of elaboration, start of simulation, run, extract, check, report, final phase.
What is a virtual sequence and a virtual sequencer?
Ans:
Virtual sequence is a container to start multiple sequences on different sequencers in the environment. This virtual sequence is usually executed by a virtual sequencer which has to handle to real sequencers. The need of virtual sequence arises when you require different sequences to be run on different env my_virtual_seq is derived from uvm_sequence just like any other sequence. A handle called p_sequencer is created within the sequence via macro `uvm_declare_p_sequencer and assigned to be run with my_virtual_sequencer.
Each sequence is started on its corresponding sequencer using the start() method.
Each sequencer is referenced by p_sequencer handle which points to the virtual sequencer.
What is the difference between `uvm_do and `uvm_send ?
Ans:
`uvm_do automatically call the create the new object creation i.e it automatically calls `uvm_create and randomize the item and send it to a sequencer. But `uvm_send is used if the data is already created and just need to be send. The main difference is `uvm_do calls the create function and creates the object, while `uvm_send does not do that.
What is the difference between uvm_transaction and uvm_sequence_item ?
Ans:
uvm_sequence_item provides the hooks for sequencer and sequence , So you can generate transaction by using sequence and sequencer , and uvm_transaction provide only basic methods like do_print and do_record etc .
What are the benefits of using UVM ?
Ans:
Modularity & reusability: the methodology is designed as modular component (driver, monitor,agents, sequencer, env, etc). Separating test with tb: tests are kept separate from the actual tb hence can be reused for different units and projects.Simulator independent: the base class lib and methodology is supported by all the simulator.Sequence based stimulus generation: sequence can be developed which include randomization, layered dequences, virtual seq, etc. which provide good control and rich stimulus.Factory mechanism: each component are registered with factory so that the factor enables them to be overridden in different test or env without changing code.
Can we have a user defined phase in UVM ?
Ans:
Creation of user-defined phases in uvm is a possibility although it hinder in complete reusability of the tb.
What is the difference between RAL backdoor and frontdoor accesses ?
Ans:
A simple explanation is that frontdoor utilizes the register peripheral bus to drive protocol transactions to the design. This is the real use case scenario where a processor core can access the register space within the design via the peripheral bus. An example would be when the design has an APB interface for its registers, and the UVM environment sends APB transactions to the design with an address and data to read/write a particular register.
The backdoor is a technique to directly put/get the value onto the register variable in the design RTL signal, for which you have to build up the hierarchical path to the registers. Backdoor does not consume any simulation time, and is faster. But it is quite insufficient to be the only mode of verification. This is usually done during the early testbench development phase or when agents that can drive transactions to the DUT are not available.
What is a phase objection ?
Ans:
There is a built-in objection for each phase which provides a way of components and object to synchronize their testing activity and indicate when it is safe to end the phase and then end the test. The component or sequence will raise a phase objection at the beginning of an activity that must be completed before the phase stops, so the objection will be dropped at the end of that activity. Once all of the raised objections are dropped, the phase terminate.
What is the difference between set_config_* and uvm_config_db ?
Ans:
Set_config*: Setting the configuration database.
Uvm_config_db #(ram_config):: set(this,”inst path”,”ram_config”, r_cfg);
Uvm_config_db: is the configuration database extends form uvm_object and we use set and get method to access the database.
What are the different factory override types ?
Ans:
Instance override by type of the component/object
Instance override by name of the component/object
Type override by type of the component/object
Name override by type of the component/object.
How can we access a DUT signal in a component or sequence ?
Ans:
Interface signal can be accessed via a virtual interface handle that points to the actual physical interface. Signals within the DUT can be accessed directly by providing a hirerchial path to the signal.
What is RALGEN and how do you use it ?
Ans:
Is a synopsys tool to generate RAL model from an IPXACT specification file. You simply have to specify a few options and select the block for which you need to generate class structure for and provide them to the tool.
What are desired and mirrored values in RAL ?
Ans:
Desired value are those that we want the design to have and can later update the design with. Mirrored values are those that reflect the latest known values in the DUT.
What are reg2bus and bus2reg functions for ?
Ans:
They are RAL functions that enable conversion from generic register content to actual bus transaction and vice versa. You have to define them based on the protocol you are dealing with by assigning the data object of the protocol with values from internal variable and vice versa.
How would you debug a config db name or path mismatch problem ?
Ans:
Use command line define +UVM_CONFIG_DB_TRACE to dump information related to all SET and GET calls done on the configuration DB. It also shows ou the path and instance that makes the call.
What are the different TB components in UVM ?
Ans:
Driver, monitor, sequencer, sequence, agent, scoreboard, test
Which phase takes more time and why ?
Ans:
Run phase takes more time because they are the major phases that consume simulation time. The time taken for each test can be different because they all the test different ascepts of a design.
How do you connect a monitor with a scoreboard ?
Ans:
You can declare the implementation of an analysis port within a scoreboard and connect the monitor’s analysis port with in the env connect method.
How do you connect driver and sequencer?
Ans:
Driver has a TLM port called seq_item_port that can be connected with the sequencer seq_item_export in an agent’s connect method.
What is uvm_config_db and uvm_resource_db ?
Ans:
The uvm_config_db class provides a convenience interface on top of the uvm_resource_db to simply the basic interface that is used for configuring uvm_component instances.
What does a sequence normally contain ?
Ans:
Sequence has a task called body() within which we can write the actual stimulus to test the design for a particular feature.
What is the difference between a deep copy and a shallow copy ?
Ans:
A shallow copy constructs a new compound object and then (to the extent possible) inserts references into it to the objects found in the original. A deep copy constructs a new compound object and then, recursively, inserts copies into it of the objects found in the original.
What is the difference between initial and final block in SystemVerilog?
Ans:
initial block:
Purpose: The initial block is used for executing a sequence of statements at the start of simulation time, before any clock cycles begin. It's primarily used for setting up initial values for variables, generating stimulus, or starting processes.
Execution: The code inside an initial block is executed once when the simulation starts. It does not repeat and only runs at time 0.
Use Case:
Initializing registers or variables.
Stimulating a design (e.g., applying test vectors).
Starting the simulation or driving specific signals for the first time.
final Block:
Purpose: The final block is used to perform tasks that should occur at the end of the simulation, just before it finishes. It's typically used for final checks, printing results, and cleaning up resources.
Execution: The code inside the final block is executed once when the simulation is about to end, after all time steps have been completed, and no more events will be scheduled.
Use Case:
Checking simulation results.
Printing final reports or log data.
Closing or releasing resources (if needed).
What is the purpose of this pointer in SystemVerilog ?
Ans:
The this keyword is used to refer to class properties, parameters and methods of the current instance. It can only be used within non-static methods, constraint and covergroup. This is basically a pre-defined object handle that refers to the object that was used to invoke the method in which this is used.
What is a virtual interface?
Ans:
Virtual interface is a variable that represents an interface instance. The virtual interface must be initialized effort using it. Virtual interface must be connected to the actual interface.
What is the difference between $random and $urandom ?
Ans:
$random: return 32 bit signed integer
$urandom: return 32 bit unsigned integer
What is the best way to avoid race conditions between DUT and testbench in a verification environment?
Ans:
Using the Program Block, Non Blocking Assignment and Clocking block.
Where is extern keyword used ?
Ans:
The extern qualifier indicates that the body of the method (its implementation) or constraint block is to be found outside the declaration. NOTE : class scope resolution operator :: should be used while defining.
What is a clocking block and why is it used ?
Ans:
A clocking block specifies timing and synchronization for a group of signals.
The clocking block specifies,
The clock event that provides a synchronization reference for DUT and testbench.
The set of signals that will be sampled and driven by the testbench.
The timing, relative to the clock event, that the testbench uses to drive and sample those signals.
Clocking block can be declared in interface, module or program block.
How can we reference variables and methods defined in the parent class from a child class?
Ans:
Super keyword
Explain the difference between pass by value and pass by reference.
Ans:
By definition, pass by value means you are making a copy in memory of the actual parameter's value that is passed in, a copy of the contents of the actual parameter.
In pass by reference (also called pass by address), a copy of the address of the actual parameter is stored. Use pass by reference when you are changing the parameter passed in by the client program.
What is the difference between rand and randc ?
Ans:
Rand: variable declared with the rand keyword are standard random variables. Their values are uniformly distributed over their rang.
Randc: variable declared with the randc keyword are random-cyclic variable that cycle through all the values in a random permutation of their declared range.
Use $urandom_range to generate 8, 16, or 32. Does this give equal probability ?
Ans:
To ensure equal probability among {8, 16, 32}, we should explicitly select from this set:
int rand_num;
initial begin
case ($urandom_range(2, 0)) // Generates 0, 1, or 2 with equal probability
0: rand_num = 8;
1: rand_num = 16;
2: rand_num = 32;
endcase
$display("Random Number: %0d", rand_num);
end
$urandom_range(2, 0) generates numbers 0, 1, or 2 with equal probability (each occurring 1/3 of the time).
Mapping {0 → 8, 1 → 16, 2 → 32} ensures that each number is selected with exactly 1/3 probability.
Thus, directly using $urandom_range(32, 8) does not give equal probability, but the case-based selection method does.
What is the difference between data types logic and reg ?
Ans:
Reg:-
Contrary to their name, regs doesn't necessarily corresponds to physical registers.
They represents data storage elements in Verilog/SystemVerilog.
They can be synthesized to FF, latch or combinational circuit (They might not be synthesizable !!!)
Wires and Regs are present from Verilog timeframe. SystemVerilog added a new data type called logic to them. So the next question is what is this logic data type and how it is different from our good old wire/reg.
Logic:-
As we have seen, reg data type is bit mis-leading in Verilog. SystemVerilog's logic data type addition is to remove the above confusion. The idea behind having a new data type called logic which at least doesn't give an impression that it is hardware synthesizable.
Logic data type doesn't permit multiple driver. It has a last assignment wins behavior in case of multiple assignment (which implies it has no hardware equivalence). Reg/Wire data type give X if multiple driver try to drive them with different value. Logic data type simply assign the last assignment value.
The next difference between reg/wire and logic is that logic can be both driven by assign block, output of a port and inside a procedural block like this.
logic a;
assign a = b ^ c; // wire style
always (c or d) a = c + d; // reg style
MyModule module(.out(a), .in(xyz)); // wire style
What is the difference between mailbox and queue ?
Ans:
A queue is just a data structure, and a mailbox is an higher level concept that is built around a combination of queues and semaphores. If you have only one process reading and writing to the data structure, there is no need to use a mailbox.
What are parameterized classes ?
Ans:
Parameterized classes are same as the parameterized modules in the verilog. Parameters are like constants local to that particular class.
The parameter value can be used to define a set of attributes in class. default values can be overridden by passing a new set of parameters during instantiation. this is called parameter overriding.
What is Class?
Ans:
1. Class is the data type which have methods and members.
2. Class is the blueprint for which memory will be created using the object.
3. For class the memory will be created during run time.
What is Inheritance?
Ans:
Creating the child class from parent class. By Adding new properties, new methods and change the behaviour of existing methods.
Inheritance provides : Reusability, TB methodology: OVM, UVM, VMM. Adding the properties to the base class by extending the base class is also known as Inheritance.
What is Polymorphism?
Ans:
Polymorphism allows a single interface to represent different underlying forms, which helps to achieve flexible, reusable, and maintainable code in object-oriented systems. The key point is that polymorphism enables one function or method to behave differently based on the actual object type being referenced or passed.
What is the Mailbox?
Ans:
Mailbox is the build in class, It works like Fifo and of infinite size.
Mailbox will have both blocking and non blocking methods.
Mailbox overcome the drawbacks of queue.
Mailbox use blocking methods to avoid the race condition.
Mailbox is used to provide the communication between transactors of inside the environment.
What is Virtual Interface?
Ans:
In system Verilog the interface are static in nature and the class are dynamic so we cannot initialize the static interface inside the dynamic class, so we use the virtual interface which refer to or point to the interface. Virtual Interface are the variables of the interface type by which we can access the interface signals.
What is Semaphore?
Ans:
Semaphore is the class which is used for the mutual exclusion and synchronization.
Methods: sem.get() and sem.put();
What is Randomization? What is the use constraint? Explain with the some example.
Ans:
Randomization is the process to randomize all the properties inside the class by randomize the class using the class handle. To verify the functionality of complex SOC we required multiple signal to be randomize. In SV randomization is the concept to randomize the multiple signal inside the class using the rand and randc randomize methods.
Class transaction();
rand bit [3:0] pktlength;
rand bit [3:0] header;
endclass
transaction trans_h();
module test;
initial
begin
int success;
trans_h =new();
success = trans_h.randomize();
end
endmodule
What is the difference between queue and mailbox?
Ans:
A mailbox is a built-in class around a queue that uses semaphores to control access to the ends of a queue. A mailbox only has FIFO element ordering whereas you can access the head, tail, or middle elements of a queue.
You typically use a mailbox when there are multiple threads reading and writing data and you need the atomic test-and-set operation of semaphore to know when the mailbox is full or empty.
In the UVM, we use a TLM FIFO which is another wrapper around a mailbox.
A queue is just a data structure, and a mailbox is an higher level concept that is built around a combination of queues and semaphores. If you have only one process reading and writing to the data structure, there is no need to use a mailbox. However if there are more than one thread, a mailbox is a convenient class to use. But if you have multiple threads, and need access to any position in the queue, you will need to write your own class to do that. The mailbox concept is in many other programming languages, so you should be able to search for more information about it.
What is the significance of virtual sequencer?
Ans:
It contain the handles of the sequencer present in the read agent and write agent. If something has to be synchronized , in general stimulus generation across different interface has to be synchronized, which is done by Virtual sequencer , virtual sequences in practical if you have two ip on soc and you want to have stimulus control , virtual sequencer , virtual sequences helps to you achieve it.
What is default sequence?
Ans:
Default sequence in UVM, is a sequence which can be executed on a particular sequencer in particular phase of uvm.
You can do this in the test build_phase() and run_phase().
There are two ways to actually call the default sequence
By using uvm_config_db#(uvm_object_wrapper)::set(this,”top.agent.myseqr.main_phase”,”default_sequence”,seq_h::type_id::get());
By using the SEQUENCE_BASE i.e seq_h=seq::type_id::create(“seq_h”);uvm_config_db#(uvm_sequence_base)::set(this,”agent.seqr.main_phase”,”default_sequence”,seq_h);
The main part is that you have to raise_objections in the sequence for running the default sequence on your particular sequencer. eg starting_phase.raise_objection(this,”start of default sequence”); starting_phase.drop_objection(this,”dropping the objection of default sequence”);
The general, application of the default sequence is for reset_sequence before starting your actual run_phase().
How to start the sequence without using the start method?
Ans:
You can register your sequence as default sequence on sequencer where you want to execute.
uvm_config_db #(uvm_object_wrapper) :: set (this,"my_env_inst.my_vir_seqr_h.main_phase", "default_sequence",my_seq:: get_type());
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