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What is p_sequencer and m_sequencer?
Ans:
p_sequencer :
The p_sequencer is a type specific sequencer pointer, created by registering the sequence to a sequencer using the `uvm_declare_p_sequencer macros. Being type specific, you will be able to access anything added to the sequencer (i.e. pointers to other sequencers, etc.).
p_sequencer will not exist if the `uvm_declare_p_sequencer macros isn’t used. (Does not exist by default).
The term p_sequencer refer to physical sequencer.
m_sequencer :
m_sequencer is the handle of uvm_sequencer_base class.
m_sequencer is present by default in every sequence (virtual sequence)
m_sequencer and p_sequencer are used for the type casting.
What is a UVM RAL model? Why is it required?
Ans:
UVM RAL as the name suggests, is a high-level object-oriented abstraction layer to access design registers. RAL model mimics the design registers and this entire model is fully configurable. Due to its abstraction behaviour, RAL model can be easily migrated from block level to system level.
RAL model mimics the design register, value by which design register is updated, with the same value RAL model register is also updated.
What is an analysis port ?
Ans:
The analysis port is used to perform non-blocking broadcasts of transactions. It is by components like monitors/drivers to publish transactions to its subscribers, which are typically scoreboards and response/coverage collectors. For each port, more than one component can be connected. Even if a component is not connected to the port, simulation can continue, unlike put/get ports where simulation is not continued.
The uvm_analysis_port consists of a single function, write(). Subscriber component should provide an implementation of write()method. UVM provides the uvm_subscriber base component to simplify this operation, so a typical analysis component would extend uvm_subscriber and its export is analysis_export.
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