Module 1 :⁠ ⁠Introduction to Verilog HDL

•     Applications of Verilog HDL

•     Verilog HDL language concept

•     Verilog language basics and constructs

•     Abstraction levels

Module 2 : ⁠Data Types

•     Type Concept

•     Nets and registers

•     Non-hardware equivalent variables

•     Arrays

Module 3 :⁠ ⁠Verilog Operators

•     Logical operators

•     Bitwise and Reduction operators

•     Concatenation and conditional

•     Relational and arithmetic

•     Shift and Equality operators

•     Operators precedence

Module 4 : Assignments

•     Type of assignments

•     Continuous assignments

•     Timing references

•     Procedures

•     Blocking and Non-Blocking assignments

•     Execution branching

•     Tasks and Functions

Module 5 :⁠ ⁠Finite State Machine

•     Basic FSM structure

•     Moore Vs Mealy

•     Common FSM coding styles

•     Registered outputs

Module 6 :⁠ ⁠Advanced Verilog for Verification

•     System Tasks

•     Compiler directives

•     Internal variable monitoring

•     File input and output

Module 7 : ⁠Synthesis Coding Style

•     Unwanted latches

•     Synthesizable operators

•     RTL coding styles

•     Synthesis errors